1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly to a semiconductor memory device of dynamic type (DRAM) having a memory cell comprising a transistor and a capacitor and method of manufacturing the same.
2. Description of the Related Art
In recent years, an area of a capacitor for electrical charge (data) has been fined in accordance with the advance of the integration of a semiconductor integrated circuit such as a DRAM. In this way, if the area of the capacitor is reduced, capacitance is reduced. As a result, there occurs a problem in the point of a software such as the contents of the memory are erroneously read or the contents of the memory are broken by an .alpha. ray.
In order to solve the above problem, there is proposed the so-called stacked capacitor structure which a MOS capacitor is stacked on a memory cell area. According to the stacked capacitor structure, a node electrode is enlarged on an isolation area, and a thickness of the electrode is increased to be box-shaped or pedestal-shaped. Whereby, the side area of the electrode can be three-dimensionally used as an area of the capacitor. Due to this, capacity, which is several times as large as a planar structure, can be obtained.
However, even in the DRAM having such a box-shaped stacked capacitor structure, since a memory cell occupied area is reduced in accordance with the advance of fining the element, it is required that the effective height of the storage node electrode be increased so as to obtain sufficient capacitance. To satisfy such a requirement, there is proposed the so-called crown structure in which the storage node electrode is cylindrically shaped to increase the area of the capacitor more. According to the crown structure, the height of the storage electrode can be set to about 2/3 of the case of the box structure in a state that the same capacitance is used. Moreover, capacitance can be set to about 1.5 times as the case of the box structure in a state that the same occupied area is used. Due to this, the use of the crown structure has been increased in the DRAM in which the enlargement of the capacity is advanced.
In any case, if the stacked capacitor structure is used, a contact path of a bit line, which is formed through an interlayer insulating film, must be deeply formed in order to connect the bit line, which is formed on the interlayer insulating film, to a wire of a lower layer of a memory cell area. Due to this, there were problems in which the formation of a contact hole becomes difficult and short-circuiting is easily generated in the vicinity of the wire of the lower layer due to over-etching.
In order to solve the above problems, there is proposed the structure in which a pad electrode having the same structure as the storage node electrode is provided in a bit line contact portion and used as a plug, whereby the depth of the contact path of the bit line is decreased (for example, Japanese Patent Application KOKAI Publication No. 3-82155). This structure is useful for the case that the box-shaped pad electrode is used. However, in a case where the pad electrode having the same structure as the cylindrical (crown) typed storage node electrode is used, the following problems will be brought about.
More specifically, if the plate electrode, serving as a pad electrode and covering the capacitor dielectric film, is formed on the cylindrical storage node electrode interposing the capacitor dielectric film therebetween and the plate electrode of the top portion of the cylindrical electrode and the capacitor dielectric film are selectively removed and the upper surface of the storage node electrode, serving as a plug, is exposed, the bit line contact area, which is electrically connected to the bit line, can be formed, but the contact resistance is increased since the contact area is small. Moreover, since the cylindrical pad electrode is used as a plug, the resistance of the plug is increased. Therefore, the resistance of the bit line contact path is more increased, and this exercises an unfavorable influence on the read/write operation.
Moreover, if materials, which have a higher dielectric constant than conventional SiN film and a SiN/SiO.sub.2 layer film, such as Ta.sub.2 O.sub.5, PZT (lead zirconate titanate), BaSrTiO.sub.3, SrTiO.sub.3 are used as the capacitor dielectric film, the following problem occurs.
More specifically, if these high dielectric film are used, metallic films such as TiN, Pt, W etc. are needed as electrodes thereof. However, since these materials cannot easily be processed with a sufficient selection ratio to the storage node electrode (for example, polysilicon is used) in selective etching, it basically becomes difficult to expose the storage node electrode.
As mentioned above, in the DRAM of the stacked capacitor memory cell structure, in the case that the cylindrical storage node structure was used, there was difficulty in forming the bit line contact in which the storage node electrode is used as a plug.
On the other hand, there is a problem in the plate electrode, which is formed on the upper portion of the storage node electrode with the capacitor dielectric film intervening therebetween. The plate electrode, which is formed around the pad electrode, is removed by etching to prevent the plate electrode from being short-circuited with the bit line contact path. In this case, there was often case in which even a part of the adjacent storage node electrode is exposed by etching and the reduction of capacitance is brought about.
Moreover, in a case where the bit line contact areas are closely formed similar to the NAND type DRAM, a groove can be formed in the surface of the plate electrode along the contact array formed by the adjacent bit line contact areas if the plate electrode around the bit line contact paths are removed by etching. As a result, the plate electrode is divided into two. In the case of the DRAM of an open bit arrangement such as an NAND type DRAM, a potential difference is generated depending on the location of the memory cell area if the plate electrode is not integrally formed, or wiring resistance exists in the plate electrode. As a result, since large noise is generated at the time of reading and writing data, and an erroneous operation occurs, it was needed that the potential of the plate electrode be fixed constant as possible.